Recently, in association with reduction in power consumption and increases in performance and speed of electronic appliances, low-power-consumption and high-speed semiconductor devices for them are demanded. In general, in order to address such a demand, semiconductor devices used in DC-DC converters of electronic appliances are required to include transistors having small ON resistance. One of methods for reducing the ON resistance of the transistors is to increase the density of the transistors arranged per unit area. Specifically, gate electrodes are arranged vertically in a semiconductor device. In the vertical gate semiconductor device in which the gate electrodes are arranged vertically, a source region and a body region are provided so as to be opposed to the upper part of the gate electrodes, and a drain region is provided so as to be opposed to the bottom of the gate electrodes.
In the case where the gate electrodes are arranged vertically, however, the uppermost faces of the vertical gate electrodes are aligned with the surface of the silicon substrate in which the source region and the body region are provided. For this reason, in connecting the electrodes to the source region or the body contact region, it is required to prevent conduction between the gate electrode and the source region or the body contact region by covering the upper part of the vertical gate electrode with a convex insulating film.
For satisfying this requirement, there has been proposed a method of manufacturing a vertical gate semiconductor device including a plurality of vertical gate electrodes arranged in parallel in which the uppermost faces of the vertical gate electrodes are recessed lower than the surface of the silicon substrate in which the source region and the body region are formed and an insulating film is filled in the recessed portion above each vertical gate electrode so that the uppermost face of the insulating film is aligned with the surface of the silicon substrate in which the source region and the body region are formed. According to this method, the vertical gate electrodes can be insulated from the source region and the body contact region without covering the upper part of each vertical gate electrodes with the convex insulting film.
A conventional vertical gate semiconductor device and a method of manufacturing it disclosed in Japanese Patent Publication No. 2662217B will be described below with reference to FIG. 19.
In the vertical gate semiconductor device shown in FIG. 19, a first conductivity type drain region 20 formed of an epitaxial layer and a second conductivity type body region 21 are formed in this order on a first conductivity type silicon substrate 19. Trenches 31 are formed so as to pass through the body region 21, and a vertical gate electrode 23 is formed in each trench 31 with an insulting material layer (a gate insulating film) 22 interposed. The vertical gate electrodes 23 are formed so as to form recessed portions in the upper parts of the trenches 31, wherein an insulating film 26 is filled in each recessed portion. A first conductivity type source region 25 is formed in the upper part of the body region 21 in the vicinity of the trenches 31 while a second conductivity type body contact region 24 is formed in a region of the upper part of the body region 21 which is adjacent to the source region 25. Hereinafter, a combination of the silicon substrate 19, the drain region 20, the body region 21, the body contact region 24, and the source region 25 is referred to as a semiconductor substrate 30. The uppermost faces of the vertical gate electrodes 23 are located lower than the surface of the semiconductor substrate 30 in which the source region 25 and the like are formed. Further, an aluminum layer 28 to be a wiring layer is formed on the semiconductor substrate 30 including the insulating film 26 with a barrier metal 27 interposed so that the wiring layer is in electrical contact with the body contact region 24 and the source region 25.
In the vertical gate semiconductor device shown in FIG. 19, the drain region 20, the body region 21, and the source region 25 are in contact with the insulating material layers 22 at the perpendicular wall faces of the trenches 31. Further, the vertical gate electrodes 23 are opposed at the upper parts thereof to the source region 25 while being opposed at the bottoms thereof to the drain region 20.
As described above, the vertical gate semiconductor device shown in FIG. 19 is a semiconductor device in which the uppermost surface of the insulating film 26 filled in the recessed portion above each vertical gate electrode 23 is aligned substantially with the surface of the semiconductor substrate 30 in which the source region 25 and the like are formed. Employment of this structure enables a masking process to be performed on the thus formed flat surface, facilitating manufacture of the semiconductor device.